Electronic digital gates can be generally divided into two classes: static gates and dynamic gates. In a static digital gate, the transistors are configured so as to maintain the state of the gate's output until one or more of the inputs to the gate change. CMOS static gates generally have slow pull-up times at their outputs due to the lower conductance of the PMOS devices. In a typical dynamic digital gate (FIG. 1), an intermediate node is pre-charged by a pull-up PMOS transistor during a first phase of a clock signal, and then selectively discharged by a pull-down logic circuit during a second subsequent phase of the clock signal. Whether or not the intermediate node is discharged will depend upon the logic states of the inputs to the pull-down logic circuit. The logic circuit is typically disabled during the first phase of the clock by an NMOS footer transistor, although the footer is unnecessary if the logic inputs are held in a state that guarantees no pull-down leg will be conducting during the pre-charge phase. The voltage state of the intermediate node is typically provided as an input to a buffer circuit or a simple (fast) static gate. The dynamic gate reduces the impact of the low conductance of the PMOS transistor by having the pull-up PMOS transistor conduct during the time the dynamic digital gate is not evaluating the inputs to the logic circuit. The pre-charge time is generally much longer than the switching time of the gate, thus accommodating the low conductance of the pull-up PMOS transistor. Thus, for the same amount of power consumption, CMOS dynamic digital gates are generally faster than CMOS static digital gates, and are preferred for use in high-speed microprocessors.
However, microprocessors are complex and often require scanning to debug and verify the functionality of the microprocessor's circuits. In a typical scanning process, the operation of the microprocessor is stopped at selected points in time by freezing the main clock signal, and the logic states of selected nodes are probed or read out for analysis by various means known to the art. During the time the main clock is stopped, the intermediate nodes that have not been previously discharged by their associated pull-down logic circuits begin slowly to lose their charged states due to leakage currents flowing in the turned-off transistors of the pull-down logic circuits, and there is a risk that incorrect data states will be read. Also, there is often a need to restart the microprocessor after the scanning process is done, and there is a risk that the microprocessor will be restarted from an erroneous state.
To address these risks, a keeper circuit is typically added to each key dynamic gate and to each key register bit. The keeper circuit senses the data state of the intermediate node, and provides a small charging current to the node when the data state is in a charged state. A keeper circuit typically comprises an inverter gate having an input coupled to the intermediate node, and an output coupled to the gate of a PMOS charging transistor. The PMOS charging transistor is configured to provide a small charge current when the output of the inverter is at a low voltage (corresponding to when the intermediate node is high). The charging current is sufficiently small that it can be overpowered by the pull-down logic circuit that is coupled to the intermediate node. The keeper circuit slows down the operation of the dynamic gate by a small amount by providing current to the intermediate node at the time the pull-down logic circuit is attempting to discharge the node. The keeper circuit also slightly increases the power dissipation of the gate. These problems are relatively minor for CMOS technologies having minimum gate lengths of 0.35 μm and above.